This invention relates to EPROM semiconductor devices, and in particular to EPROM devices having both N-channel and P-channel peripheral devices.
EPROM semiconductor circuits are well known in the art. EPROM circuits include a matrix of EPROM devices, each of which stores a bit of information, and a plurality of peripheral transistor devices. Peripheral transistors are required for such functions as row decode and column decode of the EPROM matrix, latches and drivers.
Each device, whether EPROM or peripheral, has a threshold. This threshold is the voltage level which, when applied to a FET control gate, turns the device on, allowing current to pass through its channel between its source and drain. That voltage level is determined by the sum of all the dopants in the channel region between the source and the drain and the thickness of an oxide layer between the channel and the control gate. And additionally, in the case of an EPROM device, the threshold level is determined by the charge stored on the floating gate.
In addition to having a control gate similar to the control gate of the peripheral devices, EPROM devices have a floating gate positioned below the control gate. It is this floating gate which allows the EPROM device to store charge, thereby programming the EPROM device. Conversely, when the EPROM device is unprogrammed, the floating gate is uncharged.
The architecture thus required places constraints on the size of the EPROM cell. Since the floating gate must rest directly below the control gate, both gates must be large enough to allow their proper alignment. Self-alignment of both the control gate and the floating gate allows a reduction in the size of the EPROM device.
Conventional commercial EPROM integrated circuits are NMOS wherein both the EPROM and all the peripherals are N-channel devices. The inability in practice to use P-channel transistors where their use would be beneficial has resulted in the need for a greater number of transistors (all N-channel) to perform a desired function using only N-channel transistors as well as a much larger power consumption. Peripheral circuitry could thus be reduced in size if both N-channel and P-channel transistors were used in the peripherals. Heretofore, no method has been known for integrating EPROM devices with both N-channel and P-channel transistors, that allows independently controlled threshold voltages for the three device types and/or is capable of producing self-aligned gates in the EPROM devices.
P-channel devices in a CMOS VLSI design vastly reduce the power consumption of the circuit as compared to the same circuit designed with only N-channel devices. Although it is known to combine in one chip EPROM devices, and peripheral N-MOS and P-MOS devices, the results tend to be unsatisfactory because conventional fabrication processes place serious constraints on the thresholds of those three basic FET devices.
Thus, for example, if a given threshold were required for the EPROM devices, the choices for the thresholds for one or both of the peripheral devices were constrained.
It is, therefore, an object of this invention to provide a CMOS EPROM semiconductor circuit wherein both the floating gate and the control gate of the EPROM are self-aligned.
It is a further object of this invention to provide a CMOS EPROM semiconductor circuit wherein the thresholds of the EPROM, the N-channel transistors, and the P-channel transistors may all be selected independently of each other.